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A 32K × 16 memory is to be implemented using a single decoder. The minimum number of AND gates required is:
For a 32K × 16 memory : Number of memory locations = 32 K = 32 × 1024 = 2 15 32K = 32 \times 1024 = 2^{15} Therefore, the address bus needs 15 address lines . A single decoder must be a 15 15 -to- 2 15 2^{15} decoder. Each output of the decoder is generated using an AND gate with 15 inputs . So, the minimum number of AND gates required is: 2 15 \boxed{2^{15}} Answer: (c) 2 15 2^{15} As there are 2^ 15 possible combinations of those 15 inputs: 2^ 15 AND gates 15 address lines → each AND gate has 15 inputs → 2^15 AND gates → 2^15 outputs.